Microprocessor Systems for Automobile Engine Management
Microprocessor control of a system can allow unique features to be included at minimal cost. For example, a microprocessor controlled automobile engine management system can provide control strategies that are impractical to implement using electromechanical controls.
A microprocessor has a number of components that are called by names like instruction register, decoder and ALU unit. It also has a memory unit that is either RAM or ROM.
ALU Units
The arithmetic logic unit (ALU) handles the calculations a microprocessor might need to perform. It’s typically a critical part of the CPU, as it determines how fast a processor runs. Engineers continually develop new structures to make the ALU faster, but adding complexity can also add cost, consume more energy and generate heat.
An ALU’s arithmetic circuit handles integer operations like addition, subtraction, multiplication and division. It may also include integrated overflow and underflow detectors to flag errors in arithmetic calculations. Its logic circuit handles bitwise logical operations, including AND, OR, XOR and NOT, which are essential for data manipulation and decision-making processes in computer programs. The ALU also has comparators that handle equality and relation checks, such as less than and greater than.
ALUs can also shift the arithmetic operations left and right by a definite number of bits in one operation. More complex microprocessor systems ALUs use barrel shifters to perform multiple shifts in a single cycle. Finally, ALUs provide output signals that convey the results of an operation to external circuitry. These signals often include the zero flag, carry in, negative and other status indicators.
Early microprocessors used ALUs that were limited in word width, but as transistor geometries shrunk over time, more complicated ALUs became possible. Modern ICs have wide words, which allow for large ALUs that can execute many operations in a single clock cycle.
Instruction Decoders
The instruction decoder interprets the opcode of an instruction that has been fetched from memory and generates control signals to coordinate the activities of various parts of the processor such as the Arithmetic Logic Unit (ALU), registers, and data paths. It also generates control signals to signal which bits of the microprocessor’s IR and microPC registers to load with each instruction.
For example, an x86 instruction has about 35 different bits that indicate how the instruction is to be executed and which pieces of the instruction go to where. The designer of the microprocessor sets these bits in a pattern that makes the instructions easy to decode by comparing them to a set of pre-defined blocks. This is why the opcode of a simple CPU instruction is an integer, and the opcode of more complex instructions are binary numbers.
The prefetch/predecode unit 82 may predecode instructions that are stored in instruction cache 86 by producing three bit sequences for each byte of the instructions: a start bit, an end bit, and a functional bit. This information may be used by branch prediction unit 84 to form initial branch predictions. During execution of the instructions in a program sequence, if a predicted branch instruction is incorrect, the results of the instructions that have entered the pipeline and the subsequent instructions in the ALU or other hardware may be discarded.
Memory Units
Memory units store data and instructions that the CPU needs to process. These units are volatile, meaning they lose information when the power is turned off. Computers use several types of memory units, including random access memory (RAM), read-only memory (ROM) and flash memory.
A bit is the smallest unit of information in computer memory. A bit is a binary digit that can have only two values: 1 or 0. Eight bits make up a byte, which is the smallest addressable unit in most computer systems. A byte is also called a hexadecimal, half-octet or tetrade.
Computer memory is accessed using special input lines, electronic component supplier known as address lines. These lines select one of the memory’s words based on a binary number, starting with 0 and continuing with 1, 2, 3, etc. A decoder inside the memory then opens the paths needed to retrieve that word’s data.
The control unit eventually directs memory to release the result to an output device or to a storage device. The system may also employ a technique called file caching to improve performance by temporarily moving frequently accessed data from storage to RAM, which makes it more accessible to the CPU. The CPU then returns the data to storage when it’s no longer in use. This reduces the amount of time spent retrieving data from slow storage devices and frees up space for new files.
I/O Units
An I/O unit facilitates input and output of data to and from the computer system. Input devices include keyboards and mice, while output devices include monitors and printers. I/O units are also used to convert digital data into analog signals for use with real-world devices such as audio, video or storage systems.
During operation, devices signal errors or the completion of commands via interrupts. The CPU catches these interrupts, which are usually handled by a special hardware component called an interrupt handler. The handler uses the address of a routine stored in a table, called an interrupt vector, to respond to an interrupt. Modern microprocessors support interrupt priority levels to permit handling of higher-priority interrupts over lower-priority ones.
I/O subsystems can be controlled in two ways: (1) programmed input and output; or (2) direct memory access, or DMA. Under programmed I/O, the CPU keeps its processor registers occupied for the duration of the I/O data transfer. This can be inefficient if the transfer is large or the CPU must perform other operations while waiting for a slow device to transfer data.
DMA enables I/O subsystems to transfer data with less CPU overhead. The CPU initiates the transfer, performs other operations while it waits for the device to complete the transfer, then receives an interrupt from the DMA controller when the data is ready for processing by the processor. This control method is very fast compared to programmed I/O and interrupt-driven I/O.